The present invention generally relates to implementations of decision-feedback equalizers with improved power efficiency and reduced circuit area consumption.
Today's data networks require high-speed data communication with serial link data rates above 10 Gbit/s. In this bandwidth range, a further increase of serial link data rates is challenging due to the limited general bandwidth. The general bandwidth is usually determined by dielectric losses and reflections on the transmission channel which result in a widening of the transmitted signal pulses over more than one unit interval, so that the received signal is distorted by intersymbol interference.
These signal distortions are usually compensated for by means of equalizing functions in the receiving circuitry, such as feed-forward equalizing and decision-feedback equalizing. A decision-feedback equalizer (DFE) is capable of reducing signal distortions while leaving noise or cross-talk unaffected.
In general, a decision-feedback equalizer is included in the digitalized data path at an output side of an analog-digital converter and is substantially configured to compensate for the effects of one transmitted pulse onto one or more succeeding pulses of the incoming stream of digitalized data samples. The general concept of a decision-feedback equalizer implementation is to provide at least one comparator used to translate the single pulses of the stream of digitalized data samples into a bit stream. In the comparator, the digitalized data samples are each compared with a respective variable threshold value which is generated from the history of (preceding) data samples tapped from the output of the decision-feedback equalizer. The variable threshold value is obtained by delaying the bit outputs of the decision-feedback equalizer one or more times in a number of delay stages, by weighting each of the delayed bit outputs of the decision-feedback equalizer after each stage by a predetermined (preset) coefficient and by then adding the results. The coefficients are preset with respect to a standard pulse response of the specific transmission channel. Particularly, the adding-up of the weighted delayed DFE outputs requires adding circuits which usually have a relatively high power and area consumption in an integrated circuit implementation.
An additional approach is to precompute the variable threshold values for each pattern of delayed DFE bit outputs to save the area and power impact of the line of adding circuits. This positive impact is diminished, however, as for each of the precomputed threshold values a separate comparator is required which also increases power and area consumption. Particularly, for a decision-feedback equalizer with N taps (N delay stages) using PAM-M (PAM: pulse amplitude modulation, wherein M indicates the number of data values transmitted by one data sample), a number of (M−1)×MN comparators is required. Therefore, precomputed comparator thresholds are not suitable for significantly saving area and power consumption of an implementation of the decision-feedback equalizer.
Document US2013/0287089 discloses a decision-feedback equalizer with a plurality of branches each having an adder circuit for adding a feedback signal to a received input and a latch for receiving an output of the adder circuit to provide different partial bit sequences based on a clock signal and the feedback circuit. A feedback circuit includes a multiplexer for receiving as an input the different partial bit sequences from the latch of each branch, wherein the multiplexer has a clocked select input and is configured to multiplex the different partial bit sequences of each branch to assemble a full-weight bit sequence. The feedback circuit further comprises a filter for providing a cancellation of intersymbol interference from the received input to be provided to the adder circuit of each branch.
Document U.S. Pat. No. 8,451,885 discloses an integrated circuit communication device having a filter that has a plurality of taps and is operable to process the signal and to produce a filtered signal. By means of an adapted circuitry, selected taps of the filter can be selectively adjusted based on the signal quality of the filtered signal and the power consumption of the filter, wherein the adapted circuitry is operable to receive a specified power consumption threshold and to maximize the signal quality of the filtered signal by maintaining the power consumption of the filter at or below the specified power consumption threshold.
Document US2013/0243071 discloses a decision-feedback equalizer for setting a threshold voltage for decision comparators according to a corresponding bit history of an output of the decision-feedback equalizer. Each bit history is associated with a number of taps of the decision-feedback equalizer, wherein each decision comparator is configured to provide a bit value for a current data sample based on the corresponding bit history, wherein a latch stage is provided for latching the bit value of each decision comparator. The decision-feedback equalizer has a set of interleave groups for determining a bit value of a corresponding sample in a window of samples, wherein each of the taps corresponds to a feedback path between adjacent interleave groups. By means of a multiplexing logic, a bit value of an associated one of the taps can be predictively selected based on a value of a corresponding select line in a previous interleave.
Document US2013/0243070 discloses a method for adapting one or more taps of a decision-feedback equalizer of a receiver, wherein a reference voltage for each of one or more data recovery comparators is set to a corresponding predetermined initial value. A bit value for each sample of a received signal is generated by one or more of the data recovery comparators. A window of a number of received bit samples is selected, a detected number of bits of the same logic values are tracked for each of the one or more data recovery comparators and, based on the ratio of the detected numbers, the reference voltage for the corresponding data recovery comparator is adjusted by a predetermined step amount.
Document U.S. Pat. No. 8,102,906 discloses an equalizer circuit with a number of data paths, each comprising a sensing circuitry for receiving a signal corresponding to a sequence of data digits, wherein the sensing circuitry issues at least two inputs indicative of the relative magnitude of data digits, and a multiplexer that selectively couples one of the at least two outputs to a data path output. The multiplexer in a second of the data paths is controlled, at least in part, by the output of the multiplexer in a first of the data paths, and the multiplexer in a third of the data paths is controlled, at least in part, by the output of the multiplexer in the second data path.